The timing of the
8th and 9th series, and then the timing of the fourth and fifth generation
low-power CPU chipsets is basically the same, except that the signals
transmitted between the bridge and the CPU cannot be seen and are all inside
the CPU.
I looked at the
timings of the 100 series and 300 series chipsets and they are similar, except
that the name of the bridge standby voltage has been changed and 1P8 and 1P0
are added.
Now I
will share the timing I ran based on the circuit diagram,and summarize the timing characteristics of
this type by analogy. Finally, compare it with other types of chipsets. This
can save a lot of time and master the boot timing of various notebook circuits.
Otherwise, each
circuit will be different. It is not an easy task to run the circuit and find
the timing!Of course, except for those with special chips and special circuits
such as Apple and Lenovo THINKPAD.
A Brief Description Of The Work Flow Of The ASUSF554L Board Number X555LP Motherboard:
RTC Circuit (Six Conditions)
1.
VCCRTC CMOS battery or built-in
battery supplies 3V power supply to the bridge core (this voltage cannot be
lower than 2V)
2.
RTCRST# RTC circuit reset signal
(time cannot be shorter than 18 milliseconds)
3.
SRTCRST# ME module reset signal
(time cannot be shorter than 18 milliseconds)
4.
32.768KHZ clock signal
5.
The INTVRMEN light sleep regulator
is turned on, and the internal regulator of the bridge core is controlled to
generate DCPSUS_1.05V.
6.
DSWVRMEN deep sleep regulator is
turned on (1.05V)
These
signals (the internal names of the bridge core) are all pulled up by the RTC
power supply, and the RTC circuits are basically the same.
1.
Before plugging in the power supply, the 3V button battery BAT1 passes through
the 1K resistor R2229 to generate BAT54CW, and the BAT54CW passes through the
double diode D2201 to
generate +3VA_RTC, which is sent to the AG10 ( VCCRTC ) pin
of the bridge core U0301M.
2.
+3VA_RTC provides high-level RTC_RST# to the AU7 ( RTCRST# ) pin
of the bridge core U0301E through R2226 and C2233 delay.
3.
The bridge core supplies power to the crystal oscillator X2201, which starts to
oscillate and generates 32.768KHZ to the AW5 pin (RTCX1) and AY5 pin
(RTCX2) of the bridge core.
Protective Isolation Circuit
Some protective isolation circuits are more complex and some
are simpler. To find the charging chip, search CHARGER.
4.
The power adapter is inserted into
J6001 and outputs +DC_19V. After filtering by inductors such as PL6000, PL6001,
PL6002 and capacitors such as PC6002, it is renamed A/D_DOCK_IN.
A/D_DOCK_IN is renamed P_CHG_VCC_20 through the dual diode
PD8802, which is used for the charging chip PU8800 (BQ24735 silk screen BQ735).
20 pin (VCC) supplies power; at the same time, A/D_DOCK_IN divides 2.99V
through resistors PR8814 and PR8815 and sends it to the adapter detection ACDET
pin of the charging chip; at the same time, A/D_DOCK_IN is sent to the drain of
isolation MosFet PQ8801.
5. When
the charging chip PU8800 is powered, it outputs the linear voltage VREGN=6V
from pin 16 (REGN); when the charging chip PU8800 detects that the adapter is
inserted, it outputs high-level ACOK from pin 5.
ACOK
is converted into low-level AC_IN_OC# by PQ8810A and sent to EC U3001 (IT8585E)
pin 108; when the voltage on the ACDET pin is between 2.4V and 3.15V, the ACDRV
voltage is 6V higher than CMSRC (connected to the source of the isolation MosFet
PQ8801 through the resistor PR8808), so the ACDRV generates a high The level is
connected to the gates of N-type field MosFet isolation MosFets PQ8801 and
PQ8802 to turn them on, generating a common point voltage
AC_BAT_SYS .
At the same time, AC_BAT_SYS is sent to the source of the
battery isolation MosFet PQ8803, which is slightly higher than the gate
P_CHG_BATDRV voltage to turn off the battery voltage.
When the power adapter is not plugged in, the grid of the
battery isolation MosFet PQ8803 is connected to the 11 (BATDRV) pin of the
charging chip through the 4K resistor PR8859.
The voltage of the 11-pin BATDRV is 6V higher than the
12-pin SRN (connected to the battery BAT_CON) to open the battery isolation MosFet
PQ8803 and is connected to the battery. The system power supply generates the
common point voltage AC_BAT_SYS.
Generate Standby Voltage
6.
AC_BAT_SYS is renamed P_5V3V_VIN_S
through PJP8106, and then supplies power to pin 11 (VIN) of PU8100 (UP1589QQKF)
through PR8101. PU8100 is powered. At the same time, P_5V3V_VIN_S is divided by
PR8102 and PR8103 and sent to pin 12 (EN0) of PU8100 to start working.
Output linear voltage +3VAO, +5VAO, +3VAO was
renamed +3VA by PSL8101 (+5VAO was renamed +5VA by
PSL8100 ); +3VA supplies power to pin 112 (VSTBY0) of EC U3001.
+3VA supplies power to the VIN1 pin of PU9100
(APL3533QBI-TRG) and provides bias input voltage to the BIAS pin. Pin 111 of EC
U3001 outputs high-level PS_ON to the EN1 pin of PU9100.
VOUT1 pin outputs +3VA_EC to the VSTBY of U3001 .
Pin, +3VA_EC was renamed +3VPLL to the VSTBY (PLL) pin of EC via SL3005,
+3VA_EC was renamed +3VACC to the AVCC pin of EC via SL3006.
7.
(The EC built-in crystal oscillator
generates a clock signal, and the SMCLK1 pin outputs the clock signal.) +3VA_EC
is delayed by R3212 and C3204 to generate EC_RST# and sends it to the
WRST# pin of EC U3001 for reset.
8. Pin
85 of EC U3001 sends 5VSUS_ON, which is sent to PQ8108B. Set low pin 2
(ENTRIP1) of PU8100 to start working. The output +5VO is renamed +5VSUS via
PJP8101.
+5VSUS
generates 5VSUS_PWRGD via R3060 and is sent to EC; pin 86 sends
3VSUS_ON, 3VSUS_ON . Send it to the EN2 pin of PU9100, and the VOUT2
pin outputs +3VSUS . +3VSUS generates +3VSUS_PWRGD via PQ9111
and sends it to EC.
9.
EC reads the BIOS U2803
(W25Q64FVSSIQ) program through the EC_SCE#_PCH pin of the internal FLASH ROM
module. The AC_IN_OC# output by the charging chip is sent to pin 108 of EC
U3001 (IT8585E). EC detects the adapter.
The machine does not support deep sleep and automatically
turns on the standby voltage +3VA_DSW [3VDSW_ON is sent by EC to PQ8108A and
sets low 4 of PU8100 ( ENTRIP2 ) When the pin is turned on, the
output +3VADSWO (renamed +3VA_DSW by PJP8102) is sent to the VCCDSW3_3 and
VCCSUS3_3 of the bridge core at the same time.
The EC delays sending the standby voltage good PM_RSMRST#,
and sends the DPWROK and RSMRST# to the bridge core at the same time
, notifying the bridge core that the standby voltage is normal (many
of the current new machines are: press the switch to the EC, and the EC first
sets the RSMRST# high , and then send a power-on trigger signal to the bridge
core, so as to avoid automatic power-on after the CMOS battery is powered
off) .
If the machine supports deep sleep, it will automatically
turn on the deep sleep standby voltage VCCDSW of the bridge core, and then the
EC will delay sending DPWROK to the bridge core to notify the bridge core that
the deep sleep standby voltage is good.
The bridge core sends SLP_SUS# to convert the deep sleep
standby voltage to the main standby voltage VCCSUS3_3. The main standby voltage
conversion generates RSMRST# to the bridge core to notify the bridge core that
the main standby voltage is normal.
[To determine whether the machine supports deep sleep, check
whether DPWROK and RSMRST# are connected together, or whether VCCDSW3_3 and
VCCSUS3_3 are connected together. Connecting them together is not
supported. When searching, please note that VCCDSW3_3 are the internal
names of the chip.
It depends on whether the corresponding external names (for
example, the corresponding external name of VCCDSW3_3 is +3VA_DSW) are
connected together. Or check if SLP_SUS# is left unconnected. If it is
left unconnected, it means deep sleep is not supported. 】
Trigger The Power-On Circuit
10.
Press the power button SW5601 to generate
a high-low-high PWR_SW# power-on signal to the EC (IT8585E). When the
screen-closing switch LID_SW# is normal, the EC outputs the power-on request
signal PM_PWRBTN# to the PWRBTN# pin of the bridge core.
11. The bridge core sends high-level PM_ME_SLP_LAN#
and PM_ME_SLP_A# to the EC. The EC does not use them. The SLP_S4# pin
of the bridge core sends PM_SUSC# and the SLP_S3# pin of the bridge
core sends PM_SUSB# to the EC.
12. EC receives PM_SUSC# and sends out SUSC_EC#
(turn on memory power supply), EC receives PM_SUSB# and sends out SUSB_EC#
(turn on S0 voltage, that is, secondary power supply, bridge core power supply,
bus power supply, memory VTT power supply, VDDQ, CPU core VBOOT powered).
13. SUSC_EC# to turn on +12V , +5V,
+1.35V.SUSC_EC# is sent to PQ9105 (PUMD12) to turn it on, and +12VSUS is
renamed +12V by PQ9105 . +12VSUS is renamed from +12VSUSO
through PSL8102.
+12VSUSO is boosted from the standby voltage +5VO through
PD8101, PC8129, PD8102, PC8138, etc.+12V is sent to the gate of PQ9103B through
PR9110 to turn it on.
The +5VSUS generated by the standby chip PU8100 is
renamed +5V after PQ9103B. +5V turns on the USB power supply,
etc. (It should be noted that the USB overcurrent indication signal
USB_OC#0 , USB_OC_4_5#, USB_OC_6_7# This machine is not connected to the bridge
core.
It is usually directly connected to the bridge core. If the
USB power supply is short-circuited or the charging over current pulls down the
signal, the bridge core detects it and takes corresponding actions according to
the BIOS and other programs. , For example, Lenovo G450's memory does not light
up when booting, Asus's causes power outage within 15 seconds of booting, and
some have a boot LOGO, etc.) .
Pin 83 of EC U3001 sends out 1.35V_ON, which is renamed P_DDR_1.35V_S5_10
by PR8301 and sent to pin 8 (S5) of the memory power management chip PU8300
(UP1565) to switch from S5 to S3 state,
turning on the PWM main power supply
output 1.35V to When the main power supply of the memory module is
normal (there is FB or VDDQ feedback), it returns to supply power to VDDQ and
VTTIN, and at the same time generates POK, and outputs VTTREF when VDDQ is
present.
VDDQ and VTTIN are used to generate VTT (VTT can only be
turned on after S3 is turned on). 1.35V also supplies power to the VDDQ
pin of the CPU core, which is the memory module.
14. SUSB_EC# to enable +12VS, +5VS, +3VS,
+1.5VS, +1.35VS, +1.05VS, +0.75/+0.675VS .SUSB_EC# is sent to PQ9109
(PUMD12) to turn it on, and +12VSUS is renamed +12VS by PQ9109 .
Bridge core U0301J sends MPHY_PWREN to PQ9104 (PUMD12) to
turn on, +12VSUS is renamed +12VDX by PQ9104 .+5VSUS changed its name
to +5VS after +12VS opened PQ9103A .+3VA_DSW was
renamed +3VS after opening PQ9102 (QM1830M3) by +12VS .
SUSB_EC# is sent to pin 9 (EN) of PU8404 (EM5106VT) via
PR8409 to turn on +1.5VS power supply (bridge core DAC module,
MINIPCIE pin 6).Pin 86 of EC U3001 sends out 3VSUS_ON, which is sent to
pin 13 (EN) of PU8200 (NB671LAGQ-Z) via PR8207, and outputs
+1.05VSUS. PQ9108A opened
through +12VS was renamed +1.05VS to power the bridge core;
PQ9108B opened through +12VDX was renamed +1.05VDX_MODPHY,
and renamed +1.05VS_HSIOA through SL2618 to power the bridge core.
After
SUSB_EC# , SUSC_EC# and the DDR_PG_CTRL sent by the bridge core are renamed
DDR_PG_CTRL_R signals by U1701 (74AUP1G07GW), the generated P_DDR_1.35V_S3_10
goes to the 7 (S3) pin of PU8300 to turn on the VTT +0.675V power supply of
the memory .
SUSB_EC# is sent to pin 1 (EN) of PU8701
(UP0107BMA5-00) via PR8420 to turn on the +1.2VS power
supply of LVDS.
PG, Clock, Reset Circuit
15. After each power supply is normal, the 1.35V
memory power supply POK external signal name 1.35V_PWRGD is connected through
SL5805 and +3VSUS_PWRGD to the negative terminal.
1 of D5801,
5VSUS_PWRGD is connected to the negative terminal 2 of D5801, +1.5VS_PWRGD and
+1.05VS_PWRGD are phased together. , renamed ALL_SYSTEM_PWRGD by
SL5802 , and sent to EC pin 68 (VSUS_PWRGD). EC
sends PM_PWROK, renamed PM_PWROK_PCH by R2530, to the PCH_PWROK pin
of the bridge core and connected to the APWROK pin.
16. After the bridge core receives the PCH_PWROK
pin and APWROK, it sends VCCIN_EN from the VR_EN pin to turn on the 1 (ENABLE)
pin of the CPU core power supply module PU8000 (NCP81101AMNTXG) and turn on the
CPU core power supply VBOOT (1.7-1.8V) .
17. The CPU core power supply module PU8000
sends VCCIN_VCCSENSE and VCCIN_VSSSENSE through the VSP and VSN pins to the CPU
core. After detecting that the CPU core power supply voltage is normal, the
VR_RDY pin of PU8000 sends CORE_PWRGD ( pulled up by +3VS
) to EC pin 69.
18.
After EC receives
CORE_PWRGD , it sends PM_SYSPWROK from pin 99 and renames it to
PM_SYSPWROK_PCH via SL2504 and sends it to the SYS_PWROK pin of the bridge
core.
19. After each power supply is normal (it has
nothing to do with the CPU core power supply), the single U bridge core
supplies power to the crystal oscillator X2401 and generates
a 24MHZ clock signal (if it is a single bridge core, it generates a
25MHZ clock signal).
20. After the bridge core receives the PCH_PWROK
pin and APWROK, it outputs the DRAMPWROK signal through open
drain. The 1.35V voltage is divided by the memory to obtain a 0.87-0.9V
pull-up, which is directly sent to the SM_DRAMPWROK pin of the CPU core to
notify the CPU core that the memory module is powered normally.
Note: This step is completed internally by the single U, and
there is no such signal in the actual circuit diagram.
21. Then when the power supply of VCCASW and
VCCSPI is normal, the CPU core reads the ME firmware and other BIOS programs in
the BIOS chip U2803 (search for CS#0 or CS0#) through the SPI bus to configure
the pins and initialization of the bridge core.Internal clock module.
22. After the bridge core reads the signal that
the BIOS pin configuration is successful and the clock module is initialized
successfully, it first outputs the H_CPU core PWRGD to
the PROCPWRGD pin of the CPU core, then outputs each clock,and
returns the 33M clock to its own LOOPBACK pin . (This machine
may not have a LOOPBACK pin because it is a single U).
23. After the bridge core receives
PM_SYSPWROK_PCH, it will delay sending the platform reset
signal PLT_RST# from the PLTRST# pin , directly or through U2502
conversion to generate BUF_PLT_RST# to reset other circuits, mainly providing
reset signals for each chip and slot (such as independent display, network
card, mini PCI slot, LPC bus, etc.), and at the same time, internally sends
PM_SYSRST_R# to the SYS_RESET# pin of the CPU core to reset the CPU core.
24. After the CPU core receives
PROCPWRGD, it first sends +VCCIO_OUT (+1.05V) to pull up the SVID
signal that is sent next.
Then H_CPU core_SVIDDAT and H_CPU core_SVIDALRT# are sent,
which are renamed VR_SVID_DATA and VR_SVID_ALERT# via SL0601 and R0614; H_CPU
core_SVIDCK is sent and renamed VR_SVID_CLK via SL0602; these
three SVID signals are sent to the SDIO, ALERT#, and SCLK of PU8000.
Pin, re-adjust the CPU core power supply.
Generally, the amplitude of the voltage adjustment will not
be large. If you measure it, it will still be the same voltage as before.
25. After the CPU core is powered and reset, it
goes to the bridge core through the DMI bus. The bridge core then reads the
BIOS through the SPI bus and starts self-test and code running.
The first step in the race is to reset the memory. After the
memory identification is completed through SMBUS, the bridge core sends
SM_DRAMRST# from the SM_DRAMRST# pin, which is renamed DRAMRST# via R0816 and
sent to the memory slot to reset the memory particles, and then reads the BIOS
through WE# chip select.
26. The bridge core of U0301 issues
DGPU_PWR_EN#, which is renamed to dGPU_PWRON_IO via Q7811, and dGPU_PWRON_VSG
via Q7801 to enable +1.35VSG and +3VSG;
+3VSG is renamed to dGPU_PWRON_CORE via Q7809 and Q7810, and
is renamed to dGPU_PWRON_CORE via PU8401 (MP2143DJ-LF-Z )8(EN ) pin to turn on
+0.95VSG, and PU8404 (EM5106VT) 9 (EN) pin to turn on 1.8VSG; dGPU_PWRON_CORE
was renamed dGPU_PWRON_CORE_EN by PD8501, and PU8502's 14 (EN/PSM) pin was used
to turn on +VGA_VCORE; these integrated graphics cards are powered by It is
generated after the self-test code runs through the memory.
Pay attention to the timing characteristics of the eight series
(some differences from the six series and the seven series):
1. PROCPWRGD used to be sent to the non-core
power supply pin UNCOREPWRGOOD of the CPU, but now it is sent to the power
supply pin PWRGOOD;
2.
The V5REF power supply is missing,
the VCCPLL phase-locked loop power supply of the CPU is missing, the VCCSA
housekeeper power supply of the CPU is missing, and there is only one
phase-locked loop power supply left in the bridge core, and the integrated
display power supply is missing.
3.
The CPU will output VCCIO_OUT to
pull up its SVID, adding a separate CPU reset.
Pay attention to the difference in timing between the eighth and
ninth series and the fourth and fifth generation low-power CPU chipsets:
1.
The signals transmitted between the
bridge and the CPU in the eighth and ninth series chipsets are all completed
internally in the single U of the fourth and fifth generation low-power CPU
chipsets.
2. The 8th and 9th series
chipsets issue SVID first and then reset, while in the 4th and 5th generation
low-power CPU chipsets, they reset first and then issue SVID to readjust the
CPU core power supply.
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